Oversampling analog-to-digital converters (ADC) generally consists of two parts, an analog modulator and a digital filter. The first part, the analog modulator, receives an analog signal and produces a serial data stream having a bit rate which is much greater than the Nyquist sampling frequency. The quantization noise of the analog modulator is shaped to minimize the noise in the passband of interest, at the expense of higher noise outside of this passband. This is as opposed to distributing the noise evenly between DC and the modulator sampling frequency. The digital filter portion of the ADC is operable to filter and decimate the modulator output to a lower frequency, higher resolution digital representation of the analog input. Since the modulator quantization noise is shaped, the digital filter must filter this out-of-band quantization noise and reduce the output word frequency. Decimation is a well-known technique that is utilized in most oversampling ADCs.
In a delta-sigma (also called sigma-delta) ADC, delta-sigma modulation techniques are utilized by the analog modulator. Delta-sigma ADC's are known in the art as shown, for example, in U.S. Pat. Nos. 4,746,899, 4,943,807 and 5,157,395, the disclosures of which are expressly incorporated herein by reference.
Conventional digital filters in ADCs utilize some form of digital signal processor utilizing either single or multiple stages of digital filtering. The digital filtering techniques typically utilize a finite impulse response (FIR) filter topology which generally requires a multiplier, an accumulator and stored filter coefficients that define the transfer function of the filter. The data is processed with the multiplier and accumulator utilizing the stored filter coefficients. Each set of filter coefficients is designed to provide a specific decimation rate and filter transfer function. Through decimation, the sampling rate of the signal from the delta sigma modulator is converted to a lower rate.
As integrated circuit densities increase, it is generally desirable to lessen the power requirements of any given portion of the circuitry on an integrated circuit. For a delta sigma ADC, a major part of the power requirements of the digital filter may be the power utilized to access the filter coefficients which are typically stored in a coefficient ROM. Thus, it would be desirable to lessen the power requirements of the digital filter circuitry of an ADC, and more particularly lessen the power utilized to access the coefficient ROM.